The present invention relates to a structure of a tensilely strained silicon layer on an insulator, and to a method to fabricate the same. The invention also teaches systems comprising the strained silicon layer on an insulator. Furthermore, the invention relates to a method for changing the state of strain of thin crystalline layers.
Today""s integrated circuits include a vast number of devices. Smaller devices are key to enhance performance and to improve reliability. As MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor, a name with historic connotations meaning in general an insulated gate Field-Effect-Transistor) devices are being scaled down, however, the technology becomes more complex and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. In this regard the semiconductor that has progressed the farthest is the primary semiconducting material of microelectronics: silicon (Si).
There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Several avenues are being explored for keeping device performance improvements on track. Among these is the use of tensilely strained Si as the basic semiconducting device material.
A MOSFET fabricated in tensile strained Si exhibits higher carrier mobilities than conventional MOSFET as it was shown for instance by K. Rim, et al in xe2x80x9cEnhanced performance in surface channel strained Si n and p MOSFETsxe2x80x9d, Proceedings of the Twenty Sixth International Symposium on Compound Semiconductors Berlin, Germany 22-26 Aug. 1999. The strained Si layer is typically formed by growing Si epitaxialy over a relaxed graded SiGe buffer layer as discussed in Materials Science and Engineering Reports R17, 105 (1996), by P. M. Mooney, and in U.S. Pat. No. 5,659,187 to LeGoues et al. titled: xe2x80x9cLow Defect Density/arbitrary Lattice Constant Heteroepitaxial Layersxe2x80x9d incorporated herein by reference.
While the relaxed SiGe layer is essential for straining the Si layer, this layer stack cannot be used for making silicon-on-insulator (SOI) MOSFETs. Often today""s state of the art devices operate in a semiconducting layer which is separated from the semiconducting substrate by an insulating layer. This technology is commonly knows as SOI technology. The standard method of producing SOI materials, or wafers, is called the SIMOX process. It involves the implantation of very high doses of oxygen ions at high energy into the semiconductor, and upon annealing, the oxygen forms an oxide layer under the surface of the semiconductor. In this manner one has a top semiconductor layer separated from the bulk of the substrate. However there are other methods besides SIMOX for producing SOI wafers, methods typically based on wafer bonding techniques.
A strained silicon layer on a relaxed SiGe layer is only useful for making bulk devices. Bulk devices do not have the advantages obtained for SOI devices such as reduction in the junction capacitance, and elimination of latch-up path between devices, as it is detailed, for instance in J-P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI, 2nd Ed., Kluwer Academic Press, Boston, 1997.
Ultimately, an SOI technology having a tensile strained Si layer made directly on insulator is desired, thus combining the advantages of SOI technology with the mobility enhancement obtain in strained silicon. In addition, issues related to the use of SiGe as the device substrate are eliminated. For example, cobalt disilicide forming at higher temperature in SiGe than in pure Sixe2x80x94shown by R. A Donaton et al., xe2x80x9cCo silicide formation on SiGeC/Si and SiGe/Si layersxe2x80x9d, Appl. Phys. Lett., 70, p. 1266, (1997),xe2x80x94and higher dopant diffusion are major concerns in the fabrication of a strained silicon MOSFET over SiGe.
A strained silicon layer over an isolator can be formed by wafer bonding and layer transfer. A first wafer with a strained silicon layer grown over a SiGe buffer layer is implanted with hydrogenxe2x80x94in a method called SmartCut (a registered trademark of SOITEC Corporation) as described by A. J. Auberton Herve, xe2x80x9cSOI: materials to systemsxe2x80x9d, International Electron Devices Meeting (IEDM) Technical Digest, San Francisco, p. 3-10, Dec. 1996,xe2x80x94and then flipped and bonded to a handle wafer having the isolator layer. The joint wafers are annealed to strengthen the bond and to obtain blistering at about the depth were the hydrogen was implanted. The strain silicon layer and a portion of the SiGe buffer layer are thus separated from the first wafer, and transferred by bonding to the handle wafer. There are disadvantages to this approach. First, the bonding method requires wafer bonding and layer transfer, which are expensive and relatively low yield processes. Second, the as-deposited SiGe surface is too rough for wafer bonding, which can be achieved only with very smooth and flat surfaces. As a result a long chemical mechanical polishing (CMP) step is typically applied to reduce the surface roughness to an acceptable level. Third, to obtain a strong bond the wafers need to be annealed at a temperature of over 1000xc2x0 C. However, such a high temperature will cause the strained silicon layer to relax and to diffuse Ge from the SiGe buffer into the strained silicon layer. Fourth, the lower anneal temperature that is therefore used can lead to reliability issues. Fifth, a SmartCut process in which hydrogen is implanted into the SiGe buffer layer may be difficult to control since the hydrogen will partially relocate to defects in the SiGe layer which are distant from the blistering location.
In view of the problems discussed above this invention discloses a method for forming a tensilely strained SOI layer, and discloses a structure of a tensilely strained SOI layer.
It is noted that, for the sake of simplicity, the discussion here is for the specific case of tensile strained silicon. Although strained silicon may be of special interest due to its superior properties, one skilled in the art would notice that the method is general, and applicable to other semiconductor layers, such as SiGe, SiC, GaAs, InP, InGaAs etc. Or, more generally, the method can be extended to change the state of a strain, both in a quantitative manner, for instance to increase the amount of compression or tension in a layer, and in a qualitative manner, for instance to transform from compressive to tensile strain, and to do such strain change in a wide range of materials, not necessarily only in semiconductors.
The basic invention to create a tensile strain in a Si layer on top an insulator is as follows. One starts with, or take, a standard SOI wafer with a relaxed Si layer, a well known structure in the art. Then, one forms on the top of the Si layer a relaxed SiGe layer, having a given Ge concentration at the top portion of the SiGe layer. The term relaxed means that the a layer is essentially not under strain or stress, but is able to relax by assuming its equilibrium lattice constant. In practice, however, the layer relaxation may not be full (i.e. 100% relaxation) and the actual relaxation amount depends on the method used to relax the strain in the SiGe film and on the film thickness. For example, 65% relaxation was reported in SiGe films with 30% Ge grown on silicon and relaxed by ion implantation and rapid thermal anneal (H.-J. Herzog et. al, xe2x80x9cSi/SiGe n-MODFETs on Thin SiGe Virtual Substrates Prepared by Means of He Implantationxe2x80x9d, IEEE ELECTRON DEVICE LETTERS, p. 485, 23(8), August 2002). A relaxed SiGe layer can be formed by growing a pseudomorphic SiGe layer with a uniform Ge concentration, implanting helium or hydrogen and annealing the film to relax the strain. Alternatively, the a relaxed SiGe layer can be realized by growing a thick SiGe layer with a graded Ge composition. In the later case at the interface with the Si layer the Ge concentration is relatively low, and the lattice constant is not much larger than the Si layer lattice constant, but the mismatch with the Si lattice constant can be significant toward the top of the SiGe layer, due to the higher Ge concentration found there. Next, the relaxed Si layer on top of the insulator, and the bottom portion of the relaxed SiGe layer is amorphized by ion implantation. In this manner one has a monocrystalline SiGe layer on top of an amorphous material. Following the amorphization, one re-crystallizes by solid phase epitaxy the amorphized material including the silicon-on-insulator layer, starting from the crystalline top portion of the relaxed SiGe layer. The lattice constant of the crystalline SiGe at the point of its interface with the amorphous material will have to be accommodated during the re-crystallization. Since the lattice constant at the crystalline/amorphous interface was larger than that of the Si layer, the Si layer upon re-crystallization will be in a tensile strain state due to having had to accommodate the larger lattice constant of the top part of the relaxed SiGe layer. Once the SiGe layer is removed, one obtains the tensilely strained silicon-on-insulator layer.
There can be several variations in the embodiments of creating the tensilely strained silicon-on-insulator layer.
In one alternate embodiment of the invention, the process of amorphization and solid-state epitaxy is iterated to allow a gradual building up of the strain in the SOI layer. The amorphized portion of the graded SiGe layer is increased with each iteration so that re-crystallization is commencing with a seed having ever higher Ge concentration. Successive iterations strain the SOI layer to higher levels of strain by re-crystallizing it from a region having a higher Ge concentration, thus larger lattice constant.
In yet another embodiment of the invention, the process is iterated by removing and reforming the graded SiGe layer after each re-crystallization, and each time the layer is re-formed with a higher Ge concentration. Each iteration leaves the SOI layer with a higher level of strain.
It is the object of the present invention to present a method by which tensile strain is introduced into a silicon-on-insulator layer. It is also the object of the present invention to teach a tensilely strained silicon-on-insulator, and fabrication methods thereof. It is yet another object of the present invention to teach electronic systems which comprise a tensilely strained silicon-on-insulator layer. It is a further object of the present invention to teach the generality of the method for changing a strain state of a crystalline layer on top of a support platform.